A memory device containing a non-volatile memory such as a NAND memory, is well known in the art. Referring to FIG. 1 there is shown a block level diagram of a memory device 10 of the prior art having a non-volatile memory 12 such as a NAND memory 12. A NAND controller 14 controls the operation of the NAND memory 12 to store data therein or to read data therefrom. The memory device 10 also comprises a PNOR cache 16, which is a volatile memory 16, such as PSRAM or DRAM. The cache 16 serves to store data to be written into the NAND memory 12 or to hold the data read from the NAND memory 12. The use of a memory cache 16 is advantageous for several reasons. First if NAND memory 12 is used, because the NAND memory stores a page of data at a time, if less than a page of data is desired to be stored or read, then the cache memory 16 can store the entire page of data read from (or to be written to) the NAND memory 12 from which the particular data within that page is then read from the memory device 10 or the entire page of data is written to the NAND memory 12. Second, the use of a volatile memory 16 as a cache is advantageous because typically a cache memory 16 operates faster than the non-volatile memory 12. The use of a NAND memory 12, with a NAND controller 14 and a volatile memory cache 16 functioning as a Pseudo NOR memory device is fully disclosed in U.S. 2007/0147115 A1 published Jun. 28, 2007, whose disclosure is incorporated herein by reference in its entirety.
Typically, the cache memory 16 is only a small amount of volatile memory and does not contain enough storage to store all the contents or data from the NAND memory 12. Thus, one of the functions of the NAND controller 14 is to ensure that the cache memory 16 is used most efficiently, in that the cache memory 16 should contain data that is most frequently requested thereby minimizing the number of times the NAND controller 14 must retrieve the requested data directly from the NAND memory 12. However, if multitude frequently accessed pages of NAND memory map to the same cache line, then reading one page may remove the needed page from the cache, over and over. Thus, “cache trashing” results. “Cache trashing” is the result of data in the cache memory 16 being continually changed, requiring the NAND memory 12 to be directly addressed and data read therefrom. Thus, there are occasions when read requests to the memory device 10 will result in a miss, in that the data is not found in the cache memory 16 but must be read directly from the NAND memory 12. In such event, the response of the memory device 10 is slowed. Further complicating the problem is that as multiple read requests to the same address in the NAND memory 12 occurs, excessive reading of the same location in the NAND memory 12 results. Excessive reading of the same location in a NAND memory 12 can result in read disturbance over time, and can cause read error. Thus, there is a need to minimize such read disturbance thereby reducing read errors.
In the prior art it is known that cache trashing, i.e. same data in a cache being frequently replaced, is a problem. However, cache trashing is a phenomenon known in processor caches. Further, it is well known to provide a small cache (“critical cache”) to hold frequently missed cache lines to improve performance in a high speed processor. However, such critical cache is used to improve speed and to reduce access to slower main memories in read and write operations.